mirror of
https://github.com/pine64/blisp.git
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320 lines
12 KiB
C
320 lines
12 KiB
C
// SPDX-License-Identifier: MIT
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#include <argtable3.h>
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#include <blisp.h>
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#include <blisp_easy.h>
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#include <blisp_struct.h>
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#include <inttypes.h>
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#include <stdlib.h>
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#include <string.h>
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#include "../cmd.h"
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#include "../common.h"
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#include "../util.h"
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#include "parse_file.h"
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#define REG_EXTENDED 1
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#define REG_ICASE (REG_EXTENDED << 1)
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static struct arg_rex* cmd;
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static struct arg_file* binary_to_write;
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static struct arg_str *port_name, *chip_type;
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static struct arg_lit* reset;
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static struct arg_end* end;
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static void* cmd_write_argtable[6];
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void fill_up_boot_header(struct bfl_boot_header* boot_header) {
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memcpy(boot_header->magiccode, "BFNP", 4);
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boot_header->revison = 0x01;
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memcpy(boot_header->flashCfg.magiccode, "FCFG", 4);
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boot_header->flashCfg.cfg.ioMode = 0x11;
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boot_header->flashCfg.cfg.cReadSupport = 0x00;
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boot_header->flashCfg.cfg.clkDelay = 0x01;
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boot_header->flashCfg.cfg.clkInvert = 0x01;
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boot_header->flashCfg.cfg.resetEnCmd = 0x66;
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boot_header->flashCfg.cfg.resetCmd = 0x99;
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boot_header->flashCfg.cfg.resetCreadCmd = 0xFF;
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boot_header->flashCfg.cfg.resetCreadCmdSize = 0x03;
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boot_header->flashCfg.cfg.jedecIdCmd = 0x9F;
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boot_header->flashCfg.cfg.jedecIdCmdDmyClk = 0x00;
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boot_header->flashCfg.cfg.qpiJedecIdCmd = 0x9F;
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boot_header->flashCfg.cfg.qpiJedecIdCmdDmyClk = 0x00;
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boot_header->flashCfg.cfg.sectorSize = 0x04;
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boot_header->flashCfg.cfg.mid = 0xC2;
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boot_header->flashCfg.cfg.pageSize = 0x100;
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boot_header->flashCfg.cfg.chipEraseCmd = 0xC7;
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boot_header->flashCfg.cfg.sectorEraseCmd = 0x20;
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boot_header->flashCfg.cfg.blk32EraseCmd = 0x52;
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boot_header->flashCfg.cfg.blk64EraseCmd = 0xD8;
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boot_header->flashCfg.cfg.writeEnableCmd = 0x06;
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boot_header->flashCfg.cfg.pageProgramCmd = 0x02;
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boot_header->flashCfg.cfg.qpageProgramCmd = 0x32;
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boot_header->flashCfg.cfg.qppAddrMode = 0x00;
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boot_header->flashCfg.cfg.fastReadCmd = 0x0B;
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boot_header->flashCfg.cfg.frDmyClk = 0x01;
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boot_header->flashCfg.cfg.qpiFastReadCmd = 0x0B;
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boot_header->flashCfg.cfg.qpiFrDmyClk = 0x01;
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boot_header->flashCfg.cfg.fastReadDoCmd = 0x3B;
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boot_header->flashCfg.cfg.frDoDmyClk = 0x01;
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boot_header->flashCfg.cfg.fastReadDioCmd = 0xBB;
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boot_header->flashCfg.cfg.frDioDmyClk = 0x00;
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boot_header->flashCfg.cfg.fastReadQoCmd = 0x6B;
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boot_header->flashCfg.cfg.frQoDmyClk = 0x01;
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boot_header->flashCfg.cfg.fastReadQioCmd = 0xEB;
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boot_header->flashCfg.cfg.frQioDmyClk = 0x02;
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boot_header->flashCfg.cfg.qpiFastReadQioCmd = 0xEB;
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boot_header->flashCfg.cfg.qpiFrQioDmyClk = 0x02;
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boot_header->flashCfg.cfg.qpiPageProgramCmd = 0x02;
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boot_header->flashCfg.cfg.writeVregEnableCmd = 0x50;
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boot_header->flashCfg.cfg.wrEnableIndex = 0x00;
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boot_header->flashCfg.cfg.qeIndex = 0x01;
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boot_header->flashCfg.cfg.busyIndex = 0x00;
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boot_header->flashCfg.cfg.wrEnableBit = 0x01;
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boot_header->flashCfg.cfg.qeBit = 0x01;
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boot_header->flashCfg.cfg.busyBit = 0x00;
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boot_header->flashCfg.cfg.wrEnableWriteRegLen = 0x02;
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boot_header->flashCfg.cfg.wrEnableReadRegLen = 0x01;
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boot_header->flashCfg.cfg.qeWriteRegLen = 0x02;
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boot_header->flashCfg.cfg.qeReadRegLen = 0x01;
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boot_header->flashCfg.cfg.releasePowerDown = 0xAB;
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boot_header->flashCfg.cfg.busyReadRegLen = 0x01;
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boot_header->flashCfg.cfg.readRegCmd[0] = 0x05;
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boot_header->flashCfg.cfg.readRegCmd[1] = 0x00;
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boot_header->flashCfg.cfg.readRegCmd[2] = 0x00;
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boot_header->flashCfg.cfg.readRegCmd[3] = 0x00;
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boot_header->flashCfg.cfg.writeRegCmd[0] = 0x01;
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boot_header->flashCfg.cfg.writeRegCmd[1] = 0x00;
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boot_header->flashCfg.cfg.writeRegCmd[2] = 0x00;
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boot_header->flashCfg.cfg.writeRegCmd[3] = 0x00;
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boot_header->flashCfg.cfg.enterQpi = 0x38;
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boot_header->flashCfg.cfg.exitQpi = 0xFF;
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boot_header->flashCfg.cfg.cReadMode = 0x00;
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boot_header->flashCfg.cfg.cRExit = 0xFF;
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boot_header->flashCfg.cfg.burstWrapCmd = 0x77;
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boot_header->flashCfg.cfg.burstWrapCmdDmyClk = 0x03;
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boot_header->flashCfg.cfg.burstWrapDataMode = 0x02;
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boot_header->flashCfg.cfg.burstWrapData = 0x40;
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boot_header->flashCfg.cfg.deBurstWrapCmd = 0x77;
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boot_header->flashCfg.cfg.deBurstWrapCmdDmyClk = 0x03;
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boot_header->flashCfg.cfg.deBurstWrapDataMode = 0x02;
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boot_header->flashCfg.cfg.deBurstWrapData = 0xF0;
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boot_header->flashCfg.cfg.timeEsector = 0x12C;
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boot_header->flashCfg.cfg.timeE32k = 0x4B0;
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boot_header->flashCfg.cfg.timeE64k = 0x4B0;
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boot_header->flashCfg.cfg.timePagePgm = 0x05;
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boot_header->flashCfg.cfg.timeCe = 0xFFFF;
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boot_header->flashCfg.cfg.pdDelay = 0x14;
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boot_header->flashCfg.cfg.qeData = 0x00;
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boot_header->flashCfg.crc32 = 0xE43C762A;
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boot_header->clkCfg.cfg.xtal_type = 0x01;
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boot_header->clkCfg.cfg.pll_clk = 0x04;
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boot_header->clkCfg.cfg.hclk_div = 0x00;
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boot_header->clkCfg.cfg.bclk_div = 0x01;
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boot_header->clkCfg.cfg.flash_clk_type = 0x03;
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boot_header->clkCfg.cfg.flash_clk_div = 0x00;
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boot_header->clkCfg.crc32 = 0x72127DBA;
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boot_header->bootcfg.bval.sign = 0x00;
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boot_header->bootcfg.bval.encrypt_type = 0x00;
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boot_header->bootcfg.bval.key_sel = 0x00;
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boot_header->bootcfg.bval.rsvd6_7 = 0x00;
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boot_header->bootcfg.bval.no_segment = 0x01;
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boot_header->bootcfg.bval.cache_enable = 0x01;
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boot_header->bootcfg.bval.notload_in_bootrom = 0x00;
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boot_header->bootcfg.bval.aes_region_lock = 0x00;
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boot_header->bootcfg.bval.cache_way_disable = 0x00;
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boot_header->bootcfg.bval.crc_ignore = 0x01;
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boot_header->bootcfg.bval.hash_ignore = 0x01;
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boot_header->bootcfg.bval.halt_ap = 0x00;
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boot_header->bootcfg.bval.rsvd19_31 = 0x00;
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boot_header->segment_info.segment_cnt = 0xCDA8;
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boot_header->bootentry = 0x00;
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boot_header->flashoffset = 0x2000;
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boot_header->hash[0x00] = 0xEF;
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boot_header->hash[0x01] = 0xBE;
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boot_header->hash[0x02] = 0xAD;
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boot_header->hash[0x03] = 0xDE;
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boot_header->hash[0x04] = 0x00;
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boot_header->hash[0x05] = 0x00;
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boot_header->hash[0x06] = 0x00;
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boot_header->hash[0x07] = 0x00;
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boot_header->hash[0x08] = 0x00;
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boot_header->hash[0x09] = 0x00;
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boot_header->hash[0x0a] = 0x00;
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boot_header->hash[0x0b] = 0x00;
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boot_header->hash[0x0c] = 0x00;
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boot_header->hash[0x0d] = 0x00;
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boot_header->hash[0x0e] = 0x00;
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boot_header->hash[0x0f] = 0x00;
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boot_header->hash[0x10] = 0x00;
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boot_header->hash[0x11] = 0x00;
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boot_header->hash[0x12] = 0x00;
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boot_header->hash[0x13] = 0x00;
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boot_header->hash[0x14] = 0x00;
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boot_header->hash[0x15] = 0x00;
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boot_header->hash[0x16] = 0x00;
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boot_header->hash[0x17] = 0x00;
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boot_header->hash[0x18] = 0x00;
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boot_header->hash[0x19] = 0x00;
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boot_header->hash[0x1a] = 0x00;
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boot_header->hash[0x1b] = 0x00;
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boot_header->hash[0x1c] = 0x00;
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boot_header->hash[0x1d] = 0x00;
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boot_header->hash[0x1e] = 0x00;
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boot_header->hash[0x1f] = 0x00;
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boot_header->rsv1 = 0x1000;
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boot_header->rsv2 = 0x2000;
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boot_header->crc32 = 0xDEADBEEF;
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}
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blisp_return_t blisp_flash_firmware() {
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struct blisp_device device;
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blisp_return_t ret;
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ret = blisp_common_init_device(&device, port_name, chip_type);
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if (ret != 0) {
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return ret;
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}
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if (blisp_common_prepare_flash(&device) != 0) {
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// TODO: Error handling
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goto exit1;
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}
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parsed_firmware_file_t parsed_file;
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memset(&parsed_file, 0, sizeof(parsed_file));
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int parsed_result =
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parse_firmware_file(binary_to_write->filename[0], &parsed_file);
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// If we are injecting a bootloader section, make it, erase flash, and flash
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// it. Then when we do firmware later on; it will be located afterwards
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// the header filles up to a flash erase boundry so this stack should be safe
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// __should__
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if (parsed_file.needs_boot_struct) {
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// Create a default boot header section in ram to be written out
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struct bfl_boot_header boot_header;
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fill_up_boot_header(&boot_header);
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printf("Erasing flash to flash boot header\n");
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ret = blisp_device_flash_erase(&device, 0x0000,
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sizeof(struct bfl_boot_header));
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if (ret != BLISP_OK) {
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fprintf(stderr, "Failed to erase flash.\n");
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goto exit2;
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}
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// Now burn the header
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printf("Flashing boot header...\n");
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ret = blisp_device_flash_write(&device, 0x0000, (uint8_t*)&boot_header,
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sizeof(struct bfl_boot_header));
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if (ret != BLISP_OK) {
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fprintf(stderr, "Failed to write boot header.\n");
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goto exit2;
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}
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// Move the firmware to-be-flashed beyond the boot header area
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parsed_file.payload_address += 0x2000;
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}
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// Now that optional boot header is done, we clear out the flash for the new
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// firmware; and flash it in.
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printf("Erasing flash for firmware, this might take a while...\n");
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ret = blisp_device_flash_erase(
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&device, parsed_file.payload_address,
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parsed_file.payload_address + parsed_file.payload_length);
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if (ret != BLISP_OK) {
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fprintf(stderr,
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"Failed to erase flash. Tried to erase from 0x%08X to 0x%08X\n",
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parsed_file.payload_address,
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parsed_file.payload_address + parsed_file.payload_length + 1);
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goto exit2;
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}
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printf("Flashing the firmware %d bytes @ 0x%08X...\n",
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parsed_file.payload_length, parsed_file.payload_address);
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struct blisp_easy_transport data_transport =
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blisp_easy_transport_new_from_memory(parsed_file.payload,
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parsed_file.payload_length);
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ret = blisp_easy_flash_write(
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&device, &data_transport, parsed_file.payload_address,
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parsed_file.payload_length, blisp_common_progress_callback);
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if (ret < BLISP_OK) {
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fprintf(stderr, "Failed to write app to flash.\n");
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goto exit2;
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}
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printf("Checking program...\n");
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ret = blisp_device_program_check(&device);
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if (ret != BLISP_OK) {
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fprintf(stderr, "Failed to check program.\n");
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goto exit2;
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}
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printf("Program OK!\n");
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if (reset->count > 0) {
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blisp_device_reset(&device);
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printf("Resetting the chip.\n");
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// TODO: It seems that GPIO peripheral is not reset after resetting the chip
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}
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printf("Flash complete!\n");
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exit2:
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if (parsed_file.payload != NULL)
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free(parsed_file.payload);
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exit1:
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blisp_device_close(&device);
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}
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blisp_return_t cmd_write_args_init() {
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cmd_write_argtable[0] = cmd =
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arg_rex1(NULL, NULL, "write", NULL, REG_ICASE, NULL);
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cmd_write_argtable[1] = chip_type =
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arg_str1("c", "chip", "<chip_type>", "Chip Type");
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cmd_write_argtable[2] = port_name =
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arg_str0("p", "port", "<port_name>",
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"Name/Path to the Serial Port (empty for search)");
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cmd_write_argtable[3] = reset =
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arg_lit0(NULL, "reset", "Reset chip after write");
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cmd_write_argtable[4] = binary_to_write =
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arg_file1(NULL, NULL, "<input>", "Binary to write");
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cmd_write_argtable[5] = end = arg_end(10);
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if (arg_nullcheck(cmd_write_argtable) != 0) {
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fprintf(stderr, "insufficient memory\n");
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return BLISP_ERR_OUT_OF_MEMORY;
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}
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return BLISP_OK;
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}
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void cmd_write_args_print_glossary() {
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fputs("Usage: blisp", stdout);
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arg_print_syntax(stdout, cmd_write_argtable, "\n");
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puts("Writes firmware to SPI Flash");
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arg_print_glossary(stdout, cmd_write_argtable, " %-25s %s\n");
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}
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blisp_return_t cmd_write_parse_exec(int argc, char** argv) {
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int errors = arg_parse(argc, argv, cmd_write_argtable);
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if (errors == 0) {
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return blisp_flash_firmware(); // TODO: Error code?
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} else if (cmd->count == 1) {
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cmd_write_args_print_glossary();
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return BLISP_OK;
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}
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return BLISP_ERR_INVALID_COMMAND;
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}
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void cmd_write_args_print_syntax() {
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arg_print_syntax(stdout, cmd_write_argtable, "\n");
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}
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void cmd_write_free() {
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arg_freetable(cmd_write_argtable,
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sizeof(cmd_write_argtable) / sizeof(cmd_write_argtable[0]));
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}
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struct cmd cmd_write = {"write", cmd_write_args_init, cmd_write_parse_exec,
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cmd_write_args_print_syntax, cmd_write_free};
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